CXL Memory Expansion

JH-CX5 · CXL 2.0 Type-3 · E3.S · 64–256 GB

JH Semiconductor MemoryLink CXL memory-expansion modules (JH-CX5) in CXL 2.0 Type-3, E3.S EDSFF form factor, 64/128/192/256 GB, targeting 32 GB/s — for memory expansion, pooling, and AI/cloud infrastructure. Currently a partner-controller + fixed-DRAM-BOM co-research stage.

Specification Comparison

CXL 2.0 内存扩展模组
Type: CXL 2.0
Interface: CXL 2.0 Type-3 (E3.S)
Capacity: 64 / 128 / 192 / 256GB
CXL 2.0 · 目标 32 GB/s
Fixed base model: model numbers do not change with DRAM/RCD/PMIC vendors; supply variants use only G/D and hardware-revision suffixes
Fixed BOM: no mixing of dies, RCD, PMIC or PCB within one order/batch; any change goes through PCN
G-then-D: international-vendor BOM closes compatibility and delivery first; localized BOM is qualified in parallel and released as the D version
Platform QVL: every "Intel/AMD/domestic-CPU compatible" claim maps to a specific server/board model and test record
100% inspection, per-module burn-in and batch traceability, 5-year limited warranty

Specifications as of ; see each model page and the official product guide for details.

Frequently Asked Questions

What form factor, interface and capacities does the CXL module use?

The JH-CX5 is an E3.S (EDSFF) module using CXL 2.0 Type-3 over a PCIe 5.0 x8 link with DDR5 media, offered in 64, 128, 192 and 256 GB.

What bandwidth and latency does it target?

It targets 32 GB/s bandwidth and 250–300 ns access latency, with end-to-end ECC plus CXL link CRC and DDR5-side timings of 46-45-45.

What is it for, and what platform does it need?

It serves memory expansion/pooling, AI servers, cloud and data-center use on server platforms that support CXL 2.0, with joint validation; it is currently at a partner-controller, fixed-DRAM-BOM co-research stage (P2, project-based).

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