The Analog Wall Comes First
The 14,500 MB/s maximum sequential read planned for the line is a portfolio-level envelope figure and does not belong to any single series. Still, any Gen5 platform aiming at that order of magnitude translates, on the back end, into every NAND channel running near the theoretical ceiling of its interface. Controller compute can be scaled with more cores and fixed-function acceleration; the channel interface cannot, because it is an analog problem. Every doubling of data rate halves the valid sampling window, while distortion from package parasitics, PCB trace loss and NAND input capacitance does not shrink proportionally. Whether a bandwidth target is achievable comes down to how much margin survives inside that halved window.
Training Is About Drift, Not Initial Values
Power-on write levelling and read eye training only find the optimum sampling point at ambient temperature. The hard part is drift in service: internal drive temperature can swing tens of degrees between idle and full load — the same span implied by a 6 W idle to 22 W maximum power envelope — moving thresholds and propagation delays and dragging the optimal sampling phase with them. The controller must re-run phase scans in the background and trim delay lines without interrupting host IO. The pass criterion is not "this read succeeded" but whether the remaining eye margin still covers worst-case thermal drift and worst-case media lots.
More Fan-out, Thinner Margin
The number of chip enables per channel sets capacity density. The 122.88TB maximum single-drive capacity planned for the line is likewise a portfolio-level boundary figure, and density of that order is only reachable through high fan-out. Each additional die, however, adds capacitive load and another reflection point: edges slow, overshoot worsens, jitter budget erodes. The available levers are graded on-die termination, drive strength selected per fan-out tier, and replacing long stubs with length-controlled daisy chains. All of these are margin trades — capacity bought with either peak data rate or interface power. There is no free option.
Interface Convergence Is the First Gate for an In-house Controller
The J750 and J770, both at product definition / EVT, follow an external Gen4 enterprise controller paired with in-house firmware, so channel timing parameters are set by the vendor PHY and firmware owns training policy, error recovery and retry paths. Moving toward the in-house JHC400 controller platform brings PHY behaviour and training algorithms into our own scope. The flexibility is real, but so is the transfer of verification effort: lot-to-lot timing spread and window compression across temperature bins must be covered by our own characterisation data rather than a third-party parameter table. How that roadmap is phased decides which product generation is the first where interface margin is genuinely ours to define.