Where the time actually goes
Hardware design is not what stretches an enterprise SSD program; board spins and controller bring-up usually occupy only the first stretch. Two other phases consume the time. The first is stability regression after firmware feature-complete: every item in the enterprise feature baseline — PLP, end-to-end protection with T10 DIF/DIX, multiple namespaces, NVMe-MI, TCG OPAL and Sanitize, Telemetry, online update and rollback, low-latency QoS, hot plug — must be validated individually and then in combination, because these defects typically surface only when features interact. The second is reliability and compatibility validation, where thermal cycling, accelerated TBW writing and thousands of abrupt power-loss cycles advance in weekly increments by construction. Neither phase compresses linearly by adding people. JH Semiconductor's enterprise SSD platform is currently at product-definition/EVT stage with a target window of 2026 Q4–2027 Q1, and engineering validation runs on the internal JH-E4U-C platform.
A gate is a criterion that can stop the program, not a milestone
Useful stage structure requires every gate to carry an explicit pass criterion and archivable evidence, not a review meeting and a page of minutes. The design verification gate answers whether performance, power and signal integrity meet target. After firmware freeze, only defect fixes at a defined severity may merge, and any functional change re-enters full regression. After BOM freeze, part numbers for controller, NAND, DRAM and key components are locked, and alternate parts must be re-qualified rather than waved through as equivalent. The entire purpose of a gate is to move rework cost earlier — a PLP defect found after firmware freeze costs an entire reliability test round rerun. Model names were fixed on 2026-07-22, after which changes to capacity, NAND, controller, firmware and BOM are managed only through SKU, PN, Revision and ECN: the same discipline expressed at the naming layer.
Three places things reliably go wrong
- NAND lot variation — error distributions and optimal read voltage points drift between wafer lots of the same part number, so read-retry tables and LDPC policy must be tuned per lot, or yield in a future pilot run drops without warning.
- Platform compatibility — BIOS and BMC revisions, hot-plug timing and link training behave more differently across server platforms than anyone expects, and only matrix validation covers it; sampling does not generalise.
- Test throughput — once test becomes the bottleneck, the production schedule is fiction. The in-house JH-ZS101 intelligent test system handles 600 SATA SSDs or 480 NVMe SSDs per run, integrating five processes including card initialisation and burn-in with zoned thermal control and remote power switching, precisely so this capacity exists before it is needed.
Close the productisation loop first, change controllers second
The controller roadmap therefore runs in two steps: first close a full productisation loop using an external Gen4 enterprise controller paired with in-house firmware, proving out firmware architecture, validation methodology and the production test system end to end; then evolve toward the in-house JHC400 controller platform. Front-loading system-level experience into silicon definition is the main reason for that ordering — done the other way round, architectural constraints discovered after tape-out leave almost no room to recover.