Table Size Is a Linear Function of Capacity
At the heart of the FTL is the table mapping logical pages to physical pages. With a 4KB indirection unit and a 4-byte entry, that table runs to roughly one thousandth of drive capacity. The 15.36TB point of the J750 implies a full L2P table close to 15GB, and on-drive DRAM is also typically sized at about one thousandth of capacity — apparently a match, except that the same DRAM must also hold the write cache, journals, bad-block tables and read-voltage calibration tables, so the space actually left for mapping always falls short. The constraint tightens as capacity climbs; with a planned maximum single-drive capacity of 122.88TB across the portfolio, a fully resident table is untenable under any sensible DRAM budget.
Where to Draw the Tier Boundaries
The workable approach cuts the table into fixed-size mapping pages, keeps the full table resident in NAND, caches only the active mapping pages in DRAM, and holds the hottest entries plus directory structures in controller SRAM. The tiers differ not only in capacity but in access cost: an SRAM hit lands in tens of nanoseconds, a DRAM hit in hundreds, while fetching a mapping page from NAND means a full media read, comparable in cost to a user data read.
Misses Land Directly on Tail Latency
A mapping miss turns one read into two media accesses. The QD1 read latency target planned for the J750 and J770 is 65µs, so the miss path roughly doubles it — and these events are nearly invisible in the mean, surfacing only at p99.9 and p99.99. Worse, the effect is strongly tied to working set size: once the random read address range exceeds the mapping coverage DRAM can hold, hit rate collapses across a very narrow band, appearing as a latency step the moment load grows slightly. Evaluating a mapping cache therefore cannot rest on a single average hit rate; the working set must be swept to plot hit rate and tail latency together and locate where the collapse point falls.
The Indirection Granularity Trade-off
Growing the indirection unit from 4KB to 8KB or 16KB shrinks the table proportionally, at the cost that any write smaller than the unit must read the whole unit, merge, and rewrite it — raising write amplification and write latency directly. Inside the portfolio this trade-off produces a clean division of labour. The Q7 and Q9 series address object storage, backup and archive, and AI checkpointing, workloads dominated by large sequential writes where capacity comes first and a coarse unit is affordable. The X7 and X9 series address metadata, journals, cache tiers and KV Cache, where the workload is small-block random by nature, granularity must stay fine, and hit rate outranks table footprint.
Beyond Tuning Granularity
Several further techniques are standard practice: range mapping for sequential streams, where one entry covers a long contiguous span and table footprint under sequential load can drop by an order of magnitude; prefetching mapping pages by exploiting spatial locality to pull in neighbours ahead of demand; and persisting mapping updates as a journal plus checkpoints instead of rewriting a full page per update. The benefit of each depends heavily on workload shape and must be calibrated by replaying real access traces rather than inferred from synthetic random load. All figures cited are design targets.