Three Access Patterns, Three Shapes
A training pipeline contains at least three quite different storage workloads. Sample loading is random reads across a very large number of small objects, reshuffled every epoch, with essentially no locality. Checkpointing is periodic large-block sequential writing followed by long silence. KV cache paging on the inference side is small-granularity, latency-sensitive traffic with far less tolerance for tail latency than either of the others. Covering all three with one specification means overpaying on at least one of them. Every figure quoted below is a planning target at the product-definition/EVT stage; model names are fixed, while capacity and configuration are managed through SKUs.
Sample Loading: IOPS and Latency Set GPU Idle Time
If the DataLoader workers cannot deliver the next batch, the GPU stalls. The limiter here is usually IOPS and response time rather than bandwidth — image or audio samples are often only tens to hundreds of kilobytes, and sequential throughput does not help. The CORE 7 J750 and J770 plan for 1,500 KIOPS of 4KB random read and a 65 µs QD1 average read latency, which is exactly this profile. The portfolio's planned peak sequential read of 14,500 MB/s is a different matter: it serves large-file streaming and dataset warm-up.
Checkpoints: Cost per Bit Wins
A single large-model checkpoint can be hundreds of gigabytes, and once written it is read rarely if ever. Placing that on high-endurance TLC is wasteful. The Q9 series J960Q and J960QD target AI checkpointing and very large capacity arrays with Gen5 QLC, and because the write pattern is large and sequential it avoids the small random writes QLC handles worst. The portfolio's planned per-drive capacity ceiling of 122.88TB is what turns density into a lower cost per bit.
KV Cache: Tail Latency and Endurance
Once an inference service pages attention key-value state to SSD, a single slow read shows up directly as a stutter in token output, while frequent overwriting of cache entries places real demand on endurance. The X9 series J990X and J995X are positioned for Gen5 ultra-low latency and high endurance, aimed at KV cache and real-time database tiers. The portfolio's planned write-endurance ceiling of 120 DWPD is a portfolio boundary; where an individual model lands is defined by that model's specification and SKU, so selection must check the model sheet rather than extrapolate from the boundary figure.
What This Means for Selection
Inside one training cluster these three workloads are best served by three different drive classes: high-performance TLC for the random-read-heavy tier, high-capacity QLC for cold checkpoints, and low-latency high-endurance drives for the cache tier. The real criterion is which wall each segment hits first — an idle GPU, cost per terabyte, or P99 read latency.