The Consumer Scoring Model Does Not Transfer
Running a subset of TLC blocks in single-bit mode to absorb write bursts is standard practice for lifting consumer benchmark scores: the first thirty seconds look excellent, then the curve falls away once the cache fills. Enterprise buyers apply a different test — how much bandwidth survives after hours at full load, and whether that curve is flat or stepped. For databases and virtualisation platforms, a bandwidth curve that jumps is harder to plan capacity against than one that sits lower but stays predictable.
The Cost Lands in Two Columns at Once
A single-bit cache trades capacity for speed: blocks used in single-bit mode carry one third of the user data they otherwise would. Program count matters more. Data lands in the cache first and is migrated to the multi-bit region later, so one host write becomes two NAND programs; if migration collides with garbage collection, additional valid-page relocation stacks on top. The planned J750 figure of 1 DWPD over five years and the J770 figure of 3 DWPD are budgets that cover all internal writes — migration is not exempt. The first constraint on any such design is therefore whether the endurance arithmetic balances, not what the peak looks like.
The CORE 7 Spec Sheet Says It Up Front
The J750 and J770 remain at the product-definition/EVT stage. Their media entry reads 3D enterprise TLC, and the feature baseline lists PLP, end-to-end protection, T10 DIF/DIX, multiple namespaces and low-latency QoS — with no single-bit cache mode anywhere in it. That means 7,400 MB/s sequential read, 5,500 MB/s sequential write, and random write targets of 300 KIOPS for J750 and 600 KIOPS for J770 are all quoted against one write path rather than split into in-cache and post-cache figures. Giving up the parenthesis that would have raised the headline number buys something else: the reader never has to ask which regime a number belongs to.
Steady-State Conditions Decide Whether the Comparison Holds
For cache policy differences to show up in a measurement, the conditions have to be uniform: workload-dependent preconditioning to steady state first, then sampling on a near-full drive with background activity in flight. Relax any one of empty drive, short duration or low queue depth and cache-heavy designs gain a large advantage — and all three of those relaxations are exactly what production never grants. The 65 µs QD1 average read target follows the same logic; it is only informative when background relocation is still running.
What Actually Needs Fixing Is the Footnote
The question worth asking during selection is not whether a drive carries a cache tier, but which workload, which fill level and which queue depth produced the published number. A complete footnote is what makes two drives comparable on one page; a vague one leaves even the most impressive peak as an isolated observation.