Bit Error Rate Is a Moving Curve
Raw bit error rate in NAND is not a constant. It rises with accumulated program/erase cycles, with retention time, with the number of reads a block has absorbed, and with the gap between junction temperature at read and at program. These effects compound. Error correction therefore cannot be sized against fresh-drive behaviour; it must be sized for the worst end-of-life combination, or reliability appears to fall off a cliff in years four and five.
Tier One: Hard Decision Has to Be Invisible
On the hard-decision path the controller receives one bit per cell and hands it to an LDPC decoder running min-sum iterations. This tier is pure hardware with a bounded iteration count for a simple reason: the planned QD1 4KB random read latency for J750/J770 averages 65 µs, and that covers array sense, channel transfer, correction, and host return. Only a few microseconds of that belongs to correction. Anything requiring firmware intervention breaks the budget.
Tier Two: Trading Reads for Correction Strength
When hard decision fails, the controller re-reads the page at several offset reference voltages, turning a binary verdict into a multi-level log-likelihood ratio. The added soft information buys roughly an order of magnitude in correction capability, but every extra read is a full NAND array access, pushing correction time from microseconds to hundreds of microseconds or milliseconds. Soft decision is consequently a principal source of tail latency: it exists as a backstop, and its trigger rate must stay very low.
Division of Labour with Voltage Tracking and Read Retry
The three mechanisms are sequential, not parallel. Adaptive read-voltage tracking predicts optimal reference points from a block's cycle count and retention age, suppressing errors at the source. Read Retry works at the level of re-reading with shifted voltages without engaging the decoder differently. Soft decision is the last resort. Get tracking right and the first two tiers absorb almost everything; let tracking drift and soft-decision triggers climb, degrading P99.9 immediately.
Working Backwards from the UBER Target
A target of UBER ≤1 sector per 10^18 bits read fixes the code rate, parity overhead, and iteration ceiling. Parity consumes physical NAND, so more margin means less user capacity — a direct trade between capacity and reliability. J750 (1 DWPD) and J770 (3 DWPD) share the same media and the same decoder; their difference comes from over-provisioning and write policy, while correction margin is calibrated once against J770 end-of-life conditions so both lines reuse a single validated configuration.