The Link Budget Is a System Problem
PCIe 5.0 pushes each lane to 32 GT/s and tightens the insertion-loss budget more than twofold against Gen4. The drive owns only a few centimetres of trace from connector to controller, the in-package vias and the PHY's transmit equalisation; the longer stretch belongs to the motherboard, backplane and cabling. Gen5 signal quality is therefore never a drive-only metric but a margin allocation shared by drive, backplane and platform — eye margin quoted without a platform means little.
Equalisation and Training Convergence
On the receive side CTLE flattens high-frequency channel loss, DFE cancels inter-symbol interference, and the jitter tracking bandwidth of the clock recovery loop sets tolerance to high-frequency jitter. Transmit coefficients are negotiated as presets during link training, with the LTSSM exchanging TS1/TS2 ordered sets across the phases of Recovery.Equalization until it converges. Where convergence is unstable on a given platform, the symptom is usually not a dead link but occasional Recovery counts climbing and effective bandwidth sagging — hard to attribute from throughput numbers alone.
Downshifts Are Fine; Unexplained Downshifts Are Not
Observability deserves more investment than the signalling. A link dropping to Gen4 rate or x2 width is not a disaster; having no record of why is. Firmware must log training history, correctable error counts and AER error classes into Telemetry, and combined with lane margining data that is what separates insufficient backplane trace margin from a connector contact issue from an overly aggressive retrain policy on a given platform.
Controller Roadmap and Form Factor Differences
On the Gen4 side, CORE 7 (J750 and J770) pairs an external Gen4 enterprise controller with in-house JH firmware that owns link policy, error reporting and QoS, with the long-term path leading to the in-house JHC400 controller platform. On the Gen5 side FLEX 9 uses E3.S and E1.S while TITAN 9 uses U.2/U.3; connectors and power delivery differ by form factor, so link margin is assessed separately for each. The portfolio-level sequential read ceiling is planned at 14,500 MB/s as a product-definition/EVT boundary figure; whether a given model holds its negotiated rate inside a customer chassis is a question only training logs and margining data can answer.