What Each of the Three Numbers Constrains
The power figures planned for J750/J770 during product definition/EVT are 18 W typical, 22 W maximum, and 6 W idle, and each target serves a different design decision. Typical power sizes rack-level supply and cooling capacity. Maximum power is the instantaneous ceiling the U.2 slot and backplane must cover, and it sets the trigger point for firmware power capping. Idle power drives the ongoing electricity bill at scale — a 2 W per-drive difference across a 24-bay node is 48 W of continuous load.
Why Deep Power States Rarely Pay Off in the Enterprise
NVMe lets a device define up to 32 power states (PS0 through PS31), operational and non-operational, with the deepest dropping to milliwatts. Which subset a device actually implements, and the power and entry/exit latency of each, is declared by the device to the host. The catch is that enterprise drives are seldom genuinely idle: garbage collection, wear levelling, retention refresh, and telemetry collection all pull the device back into an active state. Deep states earn their keep in client workloads; in a 7×24 server the residency time is short. Enterprise power optimisation is about performance per watt while working, not about how deeply the drive can sleep.
Where APST Fits and Where DVFS Fits
APST switches power states automatically from idle-time statistics, but both entry and exit cost time, and exit latency lands directly inside I/O response time. Latency-sensitive deployments — metadata drives, journal drives, cache tiers — commonly disable the deeper states at the driver or BIOS level. Dynamic voltage and frequency scaling is more useful in practice: the controller adjusts core clock and channel parallelism from queue depth and channel occupancy in real time, clocking down under light load and running flat out under heavy load, with far less impact on the latency distribution.
Thermal Throttling: Airflow Sets the Ceiling
In dense chassis, inlet temperature at the drive bay can exceed 40 °C. Once controller or NAND junction temperature approaches its limit, firmware must clock down or throttle, otherwise the reliability numbers stop meaning anything. The consequence is that the same U.2 15mm drive sustains noticeably different performance in a well-ventilated 2U chassis versus a high-density node. In real systems the practical power ceiling is set by cooling, not by the power supply.
The System-Level Trade
Clamp power too hard and steady-state bandwidth suffers; leave it open and dense deployments throttle repeatedly, which makes P99 worse than the conservative setting would have. The workable answer is a configurable firmware power cap with discrete levels, chosen by the integrator against measured chassis airflow rather than locked at the factory. Power levels and throttle curves are therefore a primary calibration item during platform bring-up, and nothing goes into the final specification until it has been measured on the target server models.