Sequential bandwidth is a multiplication
The J750 is planned at 7,400 MB/s sequential read and 5,500 MB/s sequential write. One qualification first: those two figures, along with the latency and IOPS numbers quoted below, are planning targets set during product definition/EVT and still awaiting measurement during platform bring-up. Neither comes from any single device. Both are the product of channel count, dies attached per channel, and planes that can operate concurrently inside each die. The interface rate and program time of one NAND die are fixed by the medium; the only thing firmware controls is how many dies are busy at any given instant.
What each layer of interleaving buys
- Channel level: physically independent paths, the cleanest parallelism dimension and the main source of raw bandwidth.
- Die level (chip-enable interleaving): dies on one channel take turns on the bus, so data transfer for one overlaps the program time of another and the channel stops idling.
- Plane level: concurrent programming inside a die, conditional on addresses meeting the alignment rules the device imposes. Miss them and the operation degrades to serial per-plane execution.
Parallelism does not buy low latency
All three layers raise throughput; none shortens a single operation. The J750 targets 65 µs average 4KB random read and 10 µs random write at QD1, and those figures are set by sense and buffer-write times in the medium — adding channels does not move them. Conversely, the 1,500 KIOPS random read target depends entirely on spreading many unrelated small requests across every die. Parallelism decides how high performance climbs as queue depth rises, not where it starts.
Why small capacity points give some of it back
Fewer dies populate fewer channels. The J750 is planned to span 1.92 to 15.36TB and the J770 1.6 to 12.8TB; within either family the low-capacity SKUs have inherently less parallelism available than the top ones. There are only two engineering options: accept and honestly document the bandwidth derating at the small points, or fill the channels with smaller dies and absorb the cost. This boundary has to be fixed during product definition — firmware tuning does not recover it later.