Threshold distributions drift in several directions
Cell threshold distributions are not static. Program/erase cycling traps charge in the tunnel oxide and widens them; long retention lets charge leak away and shifts them left; heavily read wordlines within a block creep right under read disturb. On top of that, cross-temperature effects move the optimal reference point when the junction temperature at read differs from the one at program. These mechanisms do not point the same way, which is precisely why a single fixed read-voltage table is inadequate for enterprise duty.
Retry steps are latency
Every additional retry step is a full page read, transfer and decode. The J750/J770 target 65 µs average QD1 read latency; landing on the fifth retry step multiplies that command's latency several times over, and it lands squarely in the tail, lifting P99.9. The design goal is therefore not "how many retry steps can we afford" but driving the expected number of retry steps toward zero — retry belongs on the exception path.
Aim the first read using block state
Hitting on the first read requires per-block state: erase count, timestamp of the last program, cumulative read count. That triple indexes an offset table calibrated per NAND generation, so the bias is already close to the current distribution before the read is issued. The table does not generalise — drift coefficients differ noticeably across vendors, layer counts and die configurations, so each new medium requires its own characterisation.
Division of labour with LDPC
Recovery should be an explicit ladder: hard-decision decoding first, then a bounded number of retry steps, and only then soft-decision decoding. Soft decision needs samples at several bias points to build reliability information and costs far more than one retry, so it reuses the samples the retry pass already took. Each rung carries its own latency budget and trigger counter — and the trigger rate is itself a health metric worth exporting over telemetry.
Calibrate on populations, not single drives
A drift model is fed by distributions, not sample points. The in-house JH-ZS101 test system handles 480 NVMe SSDs in parallel per run with zoned temperature control, which makes it practical to sweep raw bit error rate surfaces across cycling levels and bake conditions. The figure that has to hold is a UBER no worse than one sector per 10^18 bits read, and only large-sample statistics can support a number at that scale.