The loss budget comes before routing
PCIe 5.0 at 32 GT/s puts the Nyquist point near 16 GHz, where a trace of a given length loses noticeably more than it did at Gen4. Board design starts by decomposing the budget: package escape, in-board routing, vias, connector and far-end package — how many dB each is allowed, and how much is reserved for manufacturing spread. If the budget does not close on paper, length matching, impedance control and crosstalk work are all effort spent on nothing.
Materials and stackup trade against each other
- Dielectric: low-loss laminate improves insertion loss materially, at higher cost and with a narrower process window — lamination and drilling parameters need requalification.
- Copper roughness: skin effect turns surface roughness directly into loss at these frequencies, and low-profile foil pays for it with weaker adhesion to the dielectric.
- Layer assignment: routing differential pairs on inner layers gives a more stable reference plane, but every layer change costs return loss at the via.
These constraints pull against one another, and the optimum differs across U.2/U.3, E3.S and E1.S — board thickness and connector placement differ, so the stackup room available differs too.
Vias and connectors are the two most underestimated items
Via stubs resonate near 16 GHz, and loose control of back-drill depth turns a link that passed in simulation into one with a visible insertion-loss notch on the bench. On the connector side the issue is press-fit consistency and mating tolerance: one hand-built sample passing says nothing about volume assembly.
Leave the margin for production spread
Signal integrity conclusions from engineering samples only mean something once incoming-material and process variation are layered on top. Dielectric constant drift between laminate lots, etch-driven line width deviation and lamination thickness tolerance all eat design margin. The workable approach is sampling eye diagrams and link training results per lot on the JH-E4U-C internal engineering platform and judging on the distribution rather than a single point. The designs concerned are at the product-definition/EVT stage, with CE/FCC/RoHS/REACH certification planned, and production-consistency data accumulates in parallel with certification preparation.