Where the one-gigabyte-per-terabyte rule comes from
With 4KB mapping granularity and roughly four bytes per entry, one terabyte of user capacity needs about one gigabyte of table space — that is the entire origin of the rule of thumb. A 15.36TB J750 therefore needs DRAM in the 16GB class to keep the full table resident. Push capacity higher and the linear relationship becomes a hard wall in cost and power: a 122.88TB drive holding a fully resident 4KB-granular table would need an untenable amount of DRAM. High-capacity and QLC lines consequently move to coarser mapping units or partial residency, paying for it with stricter alignment expectations on random writes and higher overhead on small overwrite.
Three kinds of data competing for one memory
What actually coexists in DRAM has three incompatible profiles:
- The L2P table — largest, ideally fully resident. It can be rebuilt from NAND-side journals if lost; the price is recovery time.
- Metadata cache — block state, valid page counts, read counters, wear statistics. GC victim selection, wear levelling and read-disturb protection all read from it directly, so a falling hit rate does not show up as latency, it shows up as background policy making worse decisions.
- Host write buffer — the smallest of the three, and the only one that must never lose a byte once acknowledged to the host.
In practice the mapping table gets a fixed reservation, metadata scales with the capacity tier, and the write buffer is the most tightly bounded of all — sized by power-loss energy, not by performance appetite.
How much you can flush on power loss sets the buffer ceiling
Write buffer capacity is an energy calculation. At the instant of power loss, the energy held in on-board capacitors must suffice to commit every acknowledged buffer entry plus critical metadata into NAND. Flush time depends on how many channels can run concurrently and on the program mode used (usually SLC mode for speed); available energy depends on capacitance and the usable voltage window. Enlarging the buffer improves burst write behaviour, but the capacitors grow with it and consume board area, which collides directly with thermal layout in space-constrained form factors such as U.2 15mm and E1.S. It is a clean example of form factor constraining firmware parameters in the reverse direction.
The DRAM itself can be wrong
The mapping table is the index to every byte on the drive. A silently flipped bit can steer a read to an entirely wrong physical address, and the CRC on the data path will not notice — the data returned is intact, it simply does not belong to that LBA. Enterprise configurations therefore require ECC DRAM, with independent check fields on critical structures verified before use. This layer complements T10 DIF/DIX end-to-end protection rather than duplicating it: one guards the index, the other guards the payload, and dropping either leaves an open channel for silent error.