Where a 4KB Read Actually Spends Its Time
The CORE 7 J750/J770 specification defines 4KB random read latency as 65 µs average at QD1. Break that budget apart and the NAND array's own tR — sensing a page into the page register — dominates, typically tens of microseconds. The remainder is spread across doorbell write and SQ fetch, command parse and LBA-to-physical translation, channel command issue and data movement, LDPC decode, then the DMA back into host memory with CQ posting and interrupt. On a PCIe 4.0 x4 link, wire time for a single 4KB transfer is under a microsecond; at low queue depth, link bandwidth is essentially never the limiter. That is exactly why QD1 latency and the 1,500 KIOPS random read ceiling respond to two different sets of levers.
Mapping Hit Rate Shapes the Tail
A good average says nothing about the distribution. The one place a read can acquire an extra NAND access is an L2P miss: if the entry is not resident in on-drive DRAM, the controller fetches a mapping page before it can fetch the data page, doubling that request's latency. Sizing mapping residency in proportion to capacity so hot regions stay resident is, in effect, driving the probability of that tail event toward zero. The 15.36TB J750 SKU is where the constraint binds hardest, which is why it is the capacity point flagged for heavy P99.9 sampling at the current product-definition/EVT stage.
Latency Stolen by Background Work
A read does not modify the medium, but it queues behind shared resources. If the target die is mid-erase (milliseconds) or mid-program (hundreds of microseconds), the read either waits or relies on the controller's program/erase suspend capability to pre-empt. Garbage collection intensity, background refresh and read-voltage retry consume channel time the same way. Read latency is therefore not a property of the read path in isolation but an outcome of whole-drive scheduling — numbers only carry meaning when taken at steady state, on a near-full drive, with concurrent write traffic.
Fix the Conditions Before Quoting the Number
Sampling on the JH-E4U-C engineering platform is pinned to a fixed procedure: reach SNIA steady state first, then record average alongside P99 and P99.9 separately at QD1, QD32 and QD128, logging temperature and background-task duty cycle in parallel. The 65 µs figure is a specification target, and every firmware revision is regressed against it under identical conditions to see whether the distribution has shifted. Once the conditions drift, two measurements stop being comparable — a far worse outcome than a number that lands a few microseconds higher.