Register Versus Buffer: Which Layer Differs
RDIMM and LRDIMM differ not in the DRAM die but in what hangs off the bus. An RDIMM places a registering clock driver only on the command, address and clock paths; the data lines are still driven by the memory controller straight to every DRAM. An LRDIMM adds a set of data buffers on top of that, isolating the data lines as well, so the load the controller sees is collapsed to the buffer stage and the capacitive load of multiple ranks no longer stacks directly onto the bus.
Loading Decides How Much a Channel Can Carry
Load on the data lines grows with rank count, and eye margin tightens as data rate rises — that is the physical reason both DIMMs per channel and total ranks are limited. DDR5 changed several structural things: the module splits into two independent 32-bit sub-channels, the die carries on-die ECC, and power regulation moves from the motherboard to a PMIC on the module. Sub-channels rematch access granularity to burst length and raise concurrency at the same DIMM count, but they do not alter the basic constraint that data line load accumulates with rank. Platforms typically step operating speed down as DIMMs per channel and total ranks increase, so that derating rule has to be considered together with the target frequency during selection.
Why the Capacity Branch Lands on 3DS
There are two routes to higher per-module capacity: hide more ranks behind data buffers, or stack more die in package with TSVs. The DDR5 capacity branch of the company's line takes the latter, reaching 256GB per module with 3DS ECC RDIMM, where the stacking happens inside the package, the load presented to the bus stays controlled, and the RDIMM registering structure is retained. The LRDIMM branch stays within the DDR4 line, serving expansion and replacement on installed platforms alongside DDR4 RDIMM and ECC UDIMM.
Splitting Capacity-first from Latency-first
Buffering and stacking both add access latency and power, so the selection boundary can be drawn along a few lines:
- Latency first: DDR5 RDIMM 4800 and 6400, for general-purpose and inference servers that are latency sensitive with moderate per-node capacity needs.
- Capacity first: 3DS ECC RDIMM 256GB, where per-node memory capacity is a hard constraint and added latency buys density within the channel.
- Entry and single socket: ECC UDIMM 5600, with no registering stage and a more limited loading ceiling, suited to edge and entry systems.
- Height constrained: VLP ECC RDIMM, for 1U and blade chassis without the mechanical height for standard modules.
- Installed platforms: DDR4 RDIMM, ECC UDIMM and LRDIMM, for expansion without changing the platform.
Count Channels Before Choosing a Form
The right order is to fix total target capacity along with the platform's channel count and slots per channel, derive the required per-module capacity from that, then check whether that capacity point triggers a speed derate at the target frequency, and finally confirm module power and chassis airflow can support it. Skipping the first step and picking a part number straight off per-module capacity often ends with a fully populated system forced down a speed grade, delivering less real bandwidth than a slightly lower-capacity configuration that runs at full rate. CXL 2.0 memory expansion also offers a capacity path that does not consume DDR channels, suited to tiered memory cases where capacity demand exceeds channel capability and latency sensitivity is low.