Qualification is a chain, not a shipment
Getting an enterprise SSD onto a server OEM's or cloud provider's approved vendor list means clearing a sequence of explicit gates. Each gate has its own pass criteria and its own failure modes. Treating it as "send over a few drives and let them test" usually stalls at the second gate.
The four gates
- Proof of concept — does the drive enumerate correctly on the customer platform, report capacity and features properly, and clear baseline performance and compatibility;
- engineering sample testing — the customer runs its own workloads for extended periods, including steady state, power loss, hot-plug and abnormal reset;
- design verification and BOM freeze — controller, NAND generation, PCB stack-up and hold-up capacitor specification all locked, firmware version frozen;
- pilot build and small-volume production — batch consistency, line yield and end-to-end traceability.
Peak performance is rarely the blocker
Three failure causes dominate. Compatibility comes first: reference clock schemes on different backplanes, hot-plug timing, BIOS differences in recognising U.3 — all of these sink a qualification more often than IOPS does. Second is the steady-state gap: customers accept against steady-state figures, and numbers produced before preconditioning do not survive an eight-hour soak. Third is process: incomplete traceability across firmware versions, test reports and change notifications gets a submission returned at review. None of the three can be fixed by last-minute tuning.
What the freeze actually binds
BOM freeze is stronger than it sounds. Switching NAND generation, or altering the persistent layout of controller firmware, can trigger re-qualification rather than passing on a change note. This is the reason long-supply models exist — LEGACY 3 J360/J380 serve installed platforms that have already qualified and do not want to repeat the process; their value is configuration stability, not performance. The same logic applies to dual-port J760D/J780D in high-availability platforms, where replacement cost is high and change management scrutiny is correspondingly tighter.
Budget the calendar early
From proof of concept to AVL entry, the typical cycle runs in quarters and overlaps the product's own development schedule. JH Semiconductor's CORE 7 J750/J770 are at product-definition/EVT stage targeting 2026 Q4–2027 Q1; the controller path uses an external Gen4 enterprise controller with in-house firmware, evolving toward the in-house JHC400 controller platform. Qualification preparation runs in parallel with development so that the BOM freeze date lines up with the customer's validation window instead of queuing behind a finished product.