Doubling bandwidth runs into power first
PCIe 5.0 x4 takes the link from 16 to 32 GT/s, and product-level sequential read moves from the 7,400 MB/s of a J750-class Gen4 part to a 14,500 MB/s ceiling. SerDes and PHY power, however, does not scale linearly with rate, and feeding that link demands both more NAND parallelism and more controller compute. The rise in whole-drive power budget is a harder problem than the bandwidth gain suggests. The J750 sits at 18 W typical, 22 W maximum and 6 W idle; keeping a Gen5 part in that neighbourhood inside the same U.2/U.3 15mm envelope requires concessions in controller process, power conversion efficiency and throttling policy at the same time.
Thermals push the form factor toward E3.S and E1.S
U.2 depends on chassis airflow, and the drive body itself has little surface area to work with. EDSFF changes exactly that: more mounting area, a more regular presentation to the airflow, and predictable impedance from the chassis side. FLEX 9 covers both E3.S (J100E, J130E) and E1.S (J100S, J130S), matching OCP cloud datacentre and high-density node designs respectively, while TITAN 9 (J960, J980, J961, J981, J960C) stays on U.2/U.3 to serve smooth upgrades of existing chassis. At Gen5 the form factor is no longer packaging — it is a thermal design precondition.
Host-side link budget is equally tight
Allowable channel loss tightens sharply at 32 GT/s, and the full path from CPU through backplane to drive bay often needs a retimer to close the budget, which brings its own power, cost and latency. Unstable link training and silent downshifts to Gen4 or even Gen3 are the most common field issues during migration, and they usually do not originate at the drive.
Why the Gen4 lines are still growing
Migration proceeds by chassis generation, not by drive. CORE 7, TITAN 7, Q7 and X7 keep adding capacity points and form factors because a large installed base of Gen4 platforms remains in service, and fitting Gen5 drives into them yields neither the speed nor the cost back. The thirty production model codes across the portfolio span PCIe 3.0 through 5.0 for exactly this reason.